This invention relates to fabrication techniques for semi-custom integrated circuit arrays and the chips produced thereby. In particular, the invention relates to the placement of scribe lines.
The following publications are representative of the state-of-the-art for making semi-custom IC's as known to Applicant.
"The Flexible Array Technique: A Revolutionary Custom Bipolar Approach", Journal of Semi-Customs IC's, Vol. 4, No. 3, 1987, G. Gianella, discusses the shortcomings of existing linear semi-custom techniques and discloses a flexible array semi-custom technique featuring three key concepts: the use of multi-functional components called mutants; the use of an efficient universal cell; and lower silicon and design costs.
"Switch Design for Soft Configurable VLSI Systems", 1985 Chapel Hill Conference on VLSI, by Katvenis and Blatt, discloses general wafer lay out considerations, including the location of bonding pads and busses on a wafer.
"Design of VLSI Gate Array IC's", by Ernest E. Hollis, lecturer state-of-the art program, Northeastern University, pages 6-37, 1986 discusses the general principles of gate array fabrication.
"Structure of Semi-custom Integrated Circuits", by Hicks, Chapter 4, Short Run Press (England), 1983, discusses semi-custom integrated circuits including the types of semi-custom integrated circuits, fabrication steps, and layout techniques (including cell structures). A block cell structure having spaced apart cells is disclosed, see paragraph 4.2.2, wherein the spaces between the cells are used for routing inter-connections between the cells.
"Semi-custom IC Design and VLSI", edited by P. J. Hicks, Chapter 2, discusses the advantages and disadvantages of using cells in semi-custom design and fabrication.
"Gate Array Design Techniques and Applications", John W. Reid, McGraw-Hill, 1985, pages 7-9 and Chapters 3 and 9, discusses semi-custom IC fabrication technologies, including advanced cell designs (e.g., FIG. 9.3).
"A Forty K Equivalent Gate CMOS Standard Cell Chip", by Alredge, et al., IEEE 1987, Custom Integrated Circuit Conference, describes the features of a CMOS standard cell chip.
"A CMOS Master Slice Chip of Versatile Design Features", by Sporck, et al., 1984, IEEE, discusses cell arrays and a CMOS logic chip having a buffered logic cell.
"Structured Arrays--The Next Generation Gate Arrays", Svein O. Davidsen, Proceedings of the 1984 Custom Integrated Circuits Conference, May 21-23, Electron Devices Society of the IEEE, discusses structured arrays which combine the features of the gate array and standard cell approaches for application specific integrated circuits.
"Extending the Gate Array Concept Through Standard Cells", R. C. Laird, Journal of Semi-custom IC's, Vol, 4, No. 2, 1986, discusses requirements and advantages for using standard cell technology.
The following are prior art patents known to Applicant relating to making custom and semi-custom IC's.
Aneha, et al., U.S. Pat. No. 4,701,778, "Semiconductor Integrated Circuit Having Overlapping Circuit Cells", discloses the use of overlapped cells to increase packing density in a logic LSI circuit.
Kolwicz U.S. Pat. No. 4,633,571, "Method of Manufacturing a CMOS Cell Array with Transistor Isolation", discloses the use of transistor isolation and standard cells.
Sharma, et al. U.S. Pat. No. 4,575,745, "Tailorable Standard Cells and Method for Tailoring the Performance of IC Designs", discloses techniques for optimizing power consumption and IC array by providing independent control over the width of power busses and the size of active devices within cells in the IC array.
Angleton, et al. U.S. Pat. No. 4,724,531, "Gate ARray with Bi-directional Symmetry", teaches that logic functions are more easily implemented by disposing core cells within the gate array with mirror symmetry in two orthogonal directions.
Wong et al. U.S. Pat. No. 4,554,640, "Programmable Array Logic with Shared Product Terms", discloses a specific AND/OR gate circuit arrangement.
Kavlan U.S. Pat. No. 4,422,072, "Field Programmable Logic Array Circuit", discloses a technique of programmably enabling certain device pins to switch between functioning as data output pins and data input pins.
As evidenced by the foregoing references, the integrated circuit industry in general and the semi-custom industry in particular place a premium on expediting array development time and reducing associated tooling and material costs. To accomplish these goals, semi-custom chips are used. Basic components such as transistors, resistors, and capacitors are diffused ahead of time onto wafers at fixed locations, in patterns and with fixed numbers. An end user implements his custom product by designing a special metallization mask connecting only the components required for his application. Usually only one or two metal masks are required.
Such conventional semi-custom approaches provide a number of advantages: first, only one or two masks and one or two diffusion steps are required to complete the wafers, making such semi-custom techniques faster and cheaper than a conventional full scale integrated circuit development effort where 8 to 14 masks and diffusion steps are required for turn around.
Nevertheless, a basic problem remains in that the semi-custom die will rarely match the number and mix of components actually needed by the customer. As a result, quite frequently a number of components of the die will remain unused which means that silicon will be wasted. The semi-custom industry has responded to this problem by offering a family of arrays with different die sizes and consequently different component counts. However, because it is expensive to develop mask sets and special tooling for each different die size and because it is expensive to maintain an inventory of each die size, the number of different die sizes available is limited. For example, for bipolar semi-custom arrays, dies have 66, 99, 180, 240 and 360 transistors are available. For CMOS gate arrays, dies having 540, 864, 1188, 1932, 2592, 3240, etc., transistors are available. In most cases then, the user has to use an array containing more components than actually required because a smaller array is either not available or will not work. As an example, in an application requiring 250 transistor per die, an array with 360 transistors (and consequently a much bigger silicon area) must be used. Unfortunately, this mis-match between the needed component count and the available component count sometimes leads medium and high volume production and users to abandon semi-custom vendors and adopt custom, in-house fabrication.
Considering the high number of different components, like small, medium and power NPN or PNP transistors, resistors of low, medium and high value, capacitors and bonding pads, the chances of having the right number and mix of basic components in a given semi-custom array are minimal. Accordingly, prior art arrays force the use of devices big enough to contain the most critical components in the quantities required by the specific application.
The semiconductor houses, for tooling and inventory cost, offer a limited number of arrays. The possible choices of different breakdown voltages, speed, special components, different mix between components, and optional digital sections already require several different category of arrays, each one dedicated to a particular function. So it is too expensive and cumbersome to also offer a wide choice in total component count or die size in the same category of array. It is very common that a user has to use an array having many more components than he needs, because smaller arrays are not available. In many cases only one or two arrays per family are available.
The fixed mix between NPN and PNP transistors will be different from what is actually required by a customer and their location many times is not the best for routing. They do not allow a 100% utilization of all the components. Semi-custom components are larger than their full-custom counterparts. This is due to routing requirements a much more difficult and time consuming task in a semi-custom solution because of the fixed position of all the components. The transistors have multiple collector contacts, sometimes dual base contacts, base-emitter contacts far enough apart to allow a metalization line between the two and similar techniques to facilitate the metal interconnections. In a full custom design, instead, the components can be placed in the best positions for routing requirements.
All this translates into components about two times bigger, or in a high redundancy of some other form, such as resistors, cross-unders, etc. But still it is very difficult to reach a silicon utilization above 85-90%, while 75% is a more common achievement. Naturally, by using a dual metal layer this number can be increased, but this is at the expense of wafer cost and the turn-around time.
Thus there is a need to provide arrays such that the difference between the components needed by the end user and the components offered in an array or die is a minimum. Likewise there is a need to reduce the amount and variety of die sizes in inventory. There is also a need for such an array that is nevertheless prefabricated as close to finish as possible depending only on how large the custom die size must be. There is also a need for a method and system for forming a semi-custom array that uses a minimum number of masks and special tooling.